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FPGA, Jan 2011 - Apr 2011

FPGAClass: EECE 355, Digital Systems and Microcomputer
Language: VHDL, Assembly
Compiler: Quartus
Other Team Members: Sean Yang
This course has 3 major assignments:

1. Design of Arithmetic Units using Altera Quartus
Click here to download the pdf document of this assignment

2. Design of a pill counter microcontroller using VHDL
Click here to download the pdf document of this assignment

This assignment uses some design from the previous assignmnet as well as adding new parts written in VHDL (MUX, decoder, and state machine)
Below is an image of the microcontroller we use in this class, Altera DE1


3. Design of a stopwatch using Assembly Language
Click here to download the full assembly source code of this assignment.

This assignment is fully written in Assembly language. It also uses Altera DE1 board as the microcontroller, but the processor architecture is MC6811 (written by the UBC department of Electrical Engineering). You will need a special compiler to get this code working.

Operation Instruction
1. When program is loaded to the board, Press button 0 to reset the program and clock will start counting
2. Press button 3 to loop through setting hour -> minute -> and second using SW0-7
3. Turn SW8 on to start the timer, turn SW8 off will pause the timer
4. Turn SW9 on to freeze the timer screen while timer is timing (SW8 is on), turn SW9 off to continue
5. Press button 2 to reset the timer to 0

Moore's State Transition Diagram


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